1. Field of the Invention
The present invention relates to digital circuitry, and more particularly, to a delay circuit having asymmetric delay times.
2. Description of the Prior Art
In the field of digital circuitry, it is very important to control timing synchronization. General speaking, many digital circuits are controlled by an enable signal. For example, in case of memory access, in addition to a memory address to be accessed, control logic is required to generate an enable signal to an associated memory controller. Upon receiving the enable signal, the memory controller starts to access the addressed memory.
Normally, a memory controller is activated to perform an access operation if the enable signal is raised by control logic. Conversely, the memory controller stops an access operation if the enable signal is pulled down. When the enable signal is raised again by control logic, memory controller begins a next access operation. In order to prevent error operations, control logic and/or memory are usually required to wait for a predetermined amount of time to enable states of the internal circuit components to stabilize before beginning to perform a next access operation.
For this purpose, a traditional delay circuit 100 shown in FIG. 1 is adopted in the prior art for delaying an enable signal IN for a device 110 to be activated. As a result, activation timing of the device 110 is determined by a delayed enable signal IN_D. Please also refer to FIG. 2, juxtaposes the enable signal IN, and a voltage level of the delayed enable signal IN_D transiting from low to high delays for a delay time T1, which is caused by delay elements 101 to 106.
Although the delay circuit 100 guarantees that the device 100 performs a next round operation after states of internal circuits are stabilized, such a circuit wastes too much time in waiting. This is because the design of the delay circuit 100 delays the same time no matter whether the enable signal is raised or pulled down. However, in most applications, only where the enable signal IN is raised or transits from low to high voltage level, is it necessary to wait for states of circuits to stabilize. In other words, there is no need to introduce delay in the case where the enable signal IN falls or transits from a high to low voltage level. Nevertheless, as shown in FIG. 2, the delay circuit 100 shown in FIG. 1 delays the enable signal T1 time when the enable signal IN transits from a high to low voltage level. As a result, the circuit delays too much in continuous operations of the device 100 and degrades operating efficiency.